About Event

3 Days Short Term Training program “VLSI Digital Design using EDA Tools” from March 3rd - 5th, 2025 (OFFLINE).

Highlights of 3- Days Short Term Training Program
• An Insight :RTL to GDSII design flow using Synopsys EDA tools
• Simulation and Synthesis of RTL Codes – Synopsys EDA tool
• Timing and Power analysis of digital circuits - Synopsys EDA tool
• Digital Design Verification – QuestaSim

Key Takeaway
• Hands on Experience - RTL to GDS Flow - Synopsis EDA tool
• Digital Design Verification Methodologies

Target Audience
• Engineering Students (UG/PG)
• Research Scholars in VLSI domains
• Faculty Members
• Industry Professionals