One Week Short Term Training Program on Xilinx Vivado Embedded Design and Cadence IC Design 2018, MIT Academy of Engineering, Training, Pune, Maharashtra, 26th - 30th November 2018

  • Category: Training
  • Start Date: 26th November 2018
  • End Date: 30th November 2018
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One Week Short Term Training Program on Xilinx Vivado Embedded Design and Cadence IC Design 2018

Description

Dear Sir/Madam,
We are pleased to inform you that a one week Short Term Training Programme on ‘Xilinx Vivado Embedded Design and Cadence IC Design’ in association with Entuple Technologies, Banglore and CoreEL Technologies (I) Pvt. Ltd., Bangalore is being organized by the School Of Electrical engineering MITAOE, Alandi during 26th to 30th November, 2018.
The aim of the workshop is to provide hands on training to the participant on FPGA platform and Xilinx System Generator for various applications. The STTP also aims at providing Hands-on CMOS design, Simulation, Analysis, Monte Carlo Simulation, Layout, DRC, LVS, Parasitic Extraction, Post Layout simulation, design of Differential Amplifier including Spice simulation and analysis using Cadence® Virtuoso® Analog Design Environment and Mixed mode simulator.

Participants can make online Payment using Google Pay
Details: Shilpa K. Rudrawar
Mobile number: 9421851242

Registration Fee: Rs. 1000/- (for Non IET Members)
Free for IET members
Note: For further queries you can contact,

Dr. Sakhare D.Y.
Mobile No. 8149205941

Mrs. Rudrawar S.K.
Mobile No. 9421851242

Events

IET- Approved
One Week Short Term Training Program on
“Xilinx Vivado Embedded Design and Cadence IC Design”
Date: 26th to 30th November 2018
Organized by
School of Electrical Engg.
MIT Academy of Engineering Alandi Pune, 411041.

Link for Online registration

https://goo.gl/forms/H8g4wgVN4VVSy1dZ2

How to reach MIT Academy of Engineering, Pune

MIT Academy of Engineering,
Alandi Pune

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