About Event

Two-day workshop on
“CADENCE EDA Tools for SoC Chip design”
22nd & 23rd September 2022

Workshop objectives:

The aim of this workshop is to provide hands-on experience on the state-of-the-art Cadence EDA tools for VLSI Design. The participants will have an exposure to the Circuit Design & Simulation, Layout, Physical Verification (DRC, LVS), and Extraction. The workshop includes practice sessions on the Cadence design and simulation tools.

Workshops

Workshop Topics:
• Introduction to Cadence and its various tools.
• Basics of mixed signal design using Cadence Virtuoso.
• Introduction to Physical Verification, DRC/LVS by Assura.
• Implementation of NC Launch and RTL Compiler for Digital Circuit using Verilog.
• Extraction of RC Components and Generation of GDSII file.

Event Guests

Resource Person from Entuple Technologies Pvt Ltd- Bangalore

Who Can Attend:

CSE ECE Telecommunication Design

Accommodation

Food and Accommodation extra cost

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