ASIC design workshop 2018
Event Snapshot
10th - 12th September 2018
Trichy, Tamil Nadu
Workshop
Venue/Offline Mode
K Ramakrishnan College of Engineering
About Event
Opportunities in VLSI Industries & Hardware modeling using Verilog HDL & hands- on training in CAD tools.
The workshop will cover the following topics:
Combinational circuits design.
Sequential circuits design.
Synchronous circuits design.
Memories design.
FSM design.
Hardware verificationusing latest FPGA device.
Testbenches.
Design for test.
Events
Workshops
Workshops
Opportunities in VLSI Industries & Hardware modeling using Verilog HDL & hands- on training in CAD tools.
Event Guests
Mr.ananthraj,
Sr.ASIC verification engineer,
R&D department,
Sandisk,
Bangalore.
Who Can Attend:
CSE ECE EEE BioMedical DesignAccommodation
100/- per day
How to reach K Ramakrishnan College of Engineering, Trichy
Trichy central-samayapuram toll plaza(chennai or velore bus)
or
chatram-samayapuram toll plaza(perambalur bus)
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