NATIONAL WORKSHOP on Xilinx Vivado Design for Signal and Image Processing using Hardware Co-Simulation in Zynq SoC 2019

This workshop aims to provide good opportunities for the Faculty members, Research Scholars and Students, to have an insight about research issues in the design aspects of VLSI circuit methodologies and interaction with the field experts. Use Xilinx Design Constraints to communicate performance. Rapidly architect an embedded system targeting the ARM processor of Zynq Device using Vivado and IP Integrator. Extend the hardware system with Xilinx provided peripherals. Create a custom peripheral and add it to the system. Debug a design using Vivado hardware analyzer. Use Vivado HLS to generate an IP-XACT compliant hardware accelerator

WORKSHOP

Sessions will be handled by experts from CoreEL Technologies, Bangalore.

WORKSHOP

Boarding and lodging will be provided to the selected candidates in the college campus. Accommodation will be provided in the college hostel to the participants only on a chargeable basis. Participants are required to make their own arrangements for those accompanying them, if any.