Hands on Training on Full Custom Design Flow using Cadence EDA Tool 2023

The aim of this workshop is to provide hands - on experience on the state of- the art Cadence EDA tools for Digital IC Design. The participants will have an exposure to the VLSI Design flow – Overview Semicustom IC Design – Requirements and focus ASIC Design flow.

Hands on Training

ASIC Design Flow Synthesizable HDL Concepts
Technology Library – An overview
Automated RTL Synthesis using Cadence RTL Compiler
Gate Level Netlist generation Physical design flow

05.02.2023

Rs.300/-

Sri Ramakrishna Engineering College
ECE Seminar Hall

Accommodation will be provided in SREC Hostel on
prior request.