FDP on RISC-V Softcore Processor - Design and Implementation on FPGA 2023

The processor market has always been dominated by proprietary architectures that incorporate instruction sets that require licensing and payment of fees to be used. ARM is an example of a company that sells its microarchitectures to manufacturers so that they can incorporate them into their own products, and it prohibits the use of its instruction set (ISA) in other architectures without licensing. The RISC-V instruction set appeared, promising low-cost hardware and software development via the development of an open-source ISA. As a result, any project that integrates the RISC-V ISA could be made open-source or even deployed in commercial applications. In addition, use of reconfigurable architectures is more flexible for products development. Hence this program will motivate the participants to develop RISC-V softcore processor on reconfigurable (FPGA) platform.

1. Introduction to Digital Building Blocks (warm-up/walk-through)
a. Combinational Logic Design
b. Sequential Logic Design
c. Arithmetic Circuits
d. Sequential Building Blocks
e. Memory Arrays
2. RISC V - architecture
a. Assembly Language - Instructions and Operands
b. Programming - Assembly (RISC V)
c. Assembly to Machine Language
d. High level language - Compiling, Assembling,
and Loading
3. RISC V - Microarchitecture - Design and implementation
a. Architectural State and Instruction Set
b. Single-Cycle Processor - Datapath and Control
c. Multicycle Processor - Datapath and Control
d. Pipelined Processor - Datapath and Control
4. Discussion on RISC V Memory Systems

Last date for registration : 23.02.2023

Intimation of acceptance : 25.02.2023

All Category: Rs. 500/-

Myleripalayam Village, Othakkal Mandapam Post, Coimbatore - 641032, Tamilnadu, India.