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CADENCE EDA Workshop: From Schematic to GDSII File Generation 2019

Hosted by Thiagarajar College of Engineering

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Date11 Oct 201912:00 AM IST
LocationMaduraiOffline
EntryPaidExternal registration
WORKSHOPS
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About the event

The aim of this workshop is to provide hands-on experience on the state -of-the-art Cadence EDA tools for VLSI Design. The participants will have an exposure to the Circuit Design & Simulation, Layout, Physical Verification (DRC, LVS), and Extraction. The workshop includes practice sessions on the Cadence design and simulation tools (Encounter, RTL Compiler, Virtuoso, Spectre, Assura and Incisive).

Events & highlights

Workshop Topics
 Digital Design and Sign-off (Verilog/VHDL)
 Specifications
 Run Conformal Equivalence Checks
 Digital Implementation
 Synthesis and Test
 ASIC Physical Design
 Custom IC/Analog/RF Design
 Schematic Design with Virtuoso
 Virtuoso ADE Explorer S1: Set Up and Run Analog Simulations Using the Spectre Simulator Layout
 Assura Physical Verification - DRC/LVS
 Assura ParasticsExtraction
 Post Layout Simulation
 Generation of GDSII file
Benefits
 Concepts driven learning with application orientation
 Opportunity to work on industry standard design case studies
 Better preparedness to pursue final year mini/major project
 Excellent Career Oppournities in emerging Technologies- RFIC for IoT, Biomedical Applications and 5G communications

Meet the organizer

Thiagarajar College of Engineering (TCE) is as a Government Aided Autonomous Institution, established in 1957 by the philanthropist Late Karumuttu Thiagarajan Chettiar. TCE is affiliated to Anna University, Chennai, and approved by All India Council for Technical Education (AICTE). TCE offers a wide array of Undergraduate, Postgraduate and Ph.D. Programs across various disciplines of Engineering, Architecture and Science. The campus is set within a serene and eco-friendly environment surrounded by dense vegetation and best infrastructure facilities. Each academic Department at TCE is dedicated to a specific theme, fostering synergy between faculty and students in academic and research endeavours. These themes encompass diverse areas such as Eco-friendly Structures, Power and Energy, Automation, Automotive, Wireless Technologies, Distributed Computing, Database Management, Modelling and Simulation, Material Science, Green Chemistry, and Heritage. TCE has consistently embraced reforms and upgrades in its Teaching-Learning processes. Noteworthy initiatives include the implementation of a Competency-Based Curriculum and Outcome-Based Education. Since 2018, TCE has adopted the Conceive Design Implement Operate (CDIO) framework, shaping curriculum design, pedagogical methods, and assessment techniques, with adequate hands-on training to students. The institution has also launched Massive Open Online Courses (MOOCs) in 2021 and introduced the Thiagarajar Research Fellowship (TRF) scheme for Ph.D. research scholars, furthering its commitment to academic excellence and research innovation. The college maintains active industry collaborations with leading global organizations. These collaborations have resulted in the establishment of state-of-the-art laboratories, industry-oriented curriculum design, collaborative projects, professional training programs, student internships, and placements. For instance, Subject Matter Experts from TVS Motors have collaborated with TCE faculty to co-create the curriculum for Mechanical Engineering and Electrical Engineering programs, in addition to the establishment of T S Srinivasan Centre for Automotive Research.

Explore Thiagarajar College of Engineering ↗

Event type details

Workshop

Workshops

Workshop Topics
 Digital Design and Sign-off (Verilog/VHDL)
 Specifications
 Run Conformal Equivalence Checks
 Digital Implementation
 Synthesis and Test
 ASIC Physical Design
 Custom IC/Analog/RF Design
 Schematic Design with Virtuoso
 Virtuoso ADE Explorer S1: Set Up and Run Analog Simulations Using the Spectre Simulator Layout
 Assura Physical Verification - DRC/LVS
 Assura ParasticsExtraction
 Post Layout Simulation
 Generation of GDSII file
Benefits
 Concepts driven learning with application orientation
 Opportunity to work on industry standard design case studies
 Better preparedness to pursue final year mini/major project
 Excellent Career Oppournities in emerging Technologies- RFIC for IoT, Biomedical Applications and 5G communications

How to Reach

Dept. of Electronics and Communication Engg.
Thiagarajar College of Engineering
Madurai - 625 015

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