A One Day Workshop on ASIC Design for AI Applications 2026

ASIC Design for AI Applications is a one-day technical workshop organized by the Department of Electronics and Communication Engineering, Kongunadu College of Engineering and Technology. The workshop provides participants with practical exposure to ASIC design methodologies for AI applications, covering RTL modeling , architectural design, verification, synthesis, timing analysis, and optimization. Key areas include MAC units, processing elements, CNN accelerators, pipelining, parallelism, systolic arrays, memory-efficient architectures, and low-power design techniques. Participants will gain hands-on understanding of Verilog/System Verilog-based AI hardware design and Power, Performance, and Area (PPA) optimization using industry-standard EDA tools. The workshop is designed for UG/PG students, faculty members, research scholars, and industry personnel interested in AI hardware and ASIC design.

One Day Workshop

Dr. S. Ravindrakumar, B.E., M.Tech., Ph.D.
Founder & Director, IRRD Technologies, Karur, India

Last date for Registration : 29-08-2026
Intimation of Selection : 31-08-2026
(Final approved list will be informed through e-mail)

UG / PG Students : Rs.300
Faculty : Rs.400
Industry Persons : Rs.500
Pay through UPI: GPay Number: 9994930604

Bus: From Namakkal or Trichy, take a bus via the Namakka l–Trichy Main Road and get down at Kongunadu College of Engineering and Technology, Tholurpatti.

🍱 Lunch is provided free
🥤 Refreshments will be provided