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UID:eventsphere-64874@www.knowafest.com
DTSTAMP:20261008T114707Z
DTSTART:20260312T183000Z
DTEND:20260314T182959Z
SUMMARY:ChipCraft 2.0
LOCATION:Kalasalingam Academy of Research and Education\, Virudhunagar
DESCRIPTION:<p>🚀 ChipCraft 2.0 – 24hr VLSI Design Hackathon 🚀<br />
 \n<br />\n📅 13–14 March 2026 | 🏛️ DSPSD Lab 321\, Kalasalingam U
 niversity\, Krishnankoil<br />\n🎯 *Theme: RTL to Synthesis + Formal Ver
 ification<br />\n<br />\nChallenge:<br />\nGiven a real‑world problem st
 atement\, design an optimized RTL solution\, synthesize to netlist\, and v
 erify using formal methods—all within 24 hours!<br />\n<br />\nWhat you'
 ll do:<br />\n- RTL coding (Verilog/SystemVerilog)<br />\n- Logic synthesi
 s with Synopsys Design Compiler<br />\n- Formal verification with Synopsys
  VC Formal<br />\n- Generate timing/area reports and present your chip<br 
 />\n<br />\nPowered by: Synopsys Chips to Startup (C2S) Program + KARE IEE
 E EDS/SSCS<br />\n<br />\nTeam: 2–3 members<br />\nFee: ₹300/person<br
  />\nPrizes: ₹25\,000 pool (₹15k/₹7k/₹3k)<br />\nRegister: [euphor
 ia.kalasalingam.ac.in/register](https://euphoria.kalasalingam.ac.in)<br />
 \n<br />\nWho should join: ECE/EEE/CSE students with basic Verilog + Linux
  skills. Some prior Synopsys experience required—training provided!<br /
 >\n<br />\nWhy ChipCraft? Hands‑on industry VLSI flow = direct path to s
 emiconductor jobs (RTL/DFT/PD roles).<br />\n<br />\n#VLSI #ChipDesign #Ha
 ckathon #Synopsys #IEEEEDS</p>
URL:https://www.knowafest.com/chipcraft-20
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